{"id":1023,"date":"2025-10-07T11:19:52","date_gmt":"2025-10-07T16:19:52","guid":{"rendered":"https:\/\/xpeerant.com\/?post_type=awsm_job_openings&#038;p=1023"},"modified":"2025-10-07T11:19:52","modified_gmt":"2025-10-07T16:19:52","slug":"design-verification-engineer-risc-v-cpu-development","status":"publish","type":"awsm_job_openings","link":"https:\/\/xpeerant.com\/?awsm_job_openings=design-verification-engineer-risc-v-cpu-development","title":{"rendered":"Design Verification Engineer RISC-V CPU Development"},"content":{"rendered":"<article class=\"text-token-text-primary w-full\" dir=\"auto\" data-testid=\"conversation-turn-2\" data-scroll-anchor=\"true\">\n<div class=\"text-base my-auto mx-auto py-5 [--thread-content-margin:--spacing(4)] @[37rem]:[--thread-content-margin:--spacing(6)] @[72rem]:[--thread-content-margin:--spacing(16)] px-(--thread-content-margin)\">\n<div class=\"[--thread-content-max-width:32rem] @[34rem]:[--thread-content-max-width:40rem] @[64rem]:[--thread-content-max-width:48rem] mx-auto flex max-w-(--thread-content-max-width) flex-1 text-base gap-4 md:gap-5 lg:gap-6 group\/turn-messages focus-visible:outline-hidden\" tabindex=\"-1\">\n<div class=\"group\/conversation-turn relative flex w-full min-w-0 flex-col agent-turn\">\n<div class=\"relative flex-col gap-1 md:gap-3\">\n<div class=\"flex max-w-full flex-col grow\">\n<div class=\"min-h-8 text-message relative flex w-full flex-col items-end gap-2 text-start break-words whitespace-normal [.text-message+&amp;]:mt-5\" dir=\"auto\" data-message-author-role=\"assistant\" data-message-id=\"120f3856-c223-413c-b08e-6631452ae05a\" data-message-model-slug=\"gpt-4o\">\n<div class=\"flex w-full flex-col gap-1 empty:hidden first:pt-[3px]\">\n<div class=\"markdown prose dark:prose-invert w-full break-words light\">\n<p data-start=\"138\" data-end=\"296\"><strong data-start=\"138\" data-end=\"210\">Design Verification Engineer RISC-V CPU Development<\/strong><\/p>\n<p><br data-start=\"210\" data-end=\"213\" \/>Are you passionate about cutting-edge CPU architecture and ready to take your verification skills to the next level? We re partnering with a global leader in RISC-V processor design to find talented Design Verification Engineers to join their high-impact VLSI team.You ll work alongside seasoned architects and engineers to verify next-generation RISC-V CPU cores, develop test benches from the ground up, and help shape the future of custom CPU IP.<\/div>\n<div class=\"markdown prose dark:prose-invert w-full break-words light\">\n<h5 data-start=\"829\" data-end=\"857\"><\/h5>\n<h5 data-start=\"829\" data-end=\"857\"><strong>Key Responsibilities:<\/strong><\/h5>\n<ul data-start=\"858\" data-end=\"1249\">\n<li data-start=\"858\" data-end=\"937\">Collaborate with engineers to define and implement verification methodologies<\/li>\n<li data-start=\"938\" data-end=\"1013\">Analyze CPU architecture and memory subsystems for comprehensive coverage<\/li>\n<li data-start=\"1014\" data-end=\"1101\">Perform hands-on verification, including regression testing, debugging, and reporting<\/li>\n<li data-start=\"1102\" data-end=\"1165\">Build test benches and verification environments from scratch<\/li>\n<li data-start=\"1166\" data-end=\"1202\">Guide and support junior engineers<\/li>\n<li data-start=\"1203\" data-end=\"1249\">Document verification processes and outcomes<\/li>\n<\/ul>\n<h5 data-start=\"1251\" data-end=\"1278\"><strong>Basic Qualifications:<\/strong><\/h5>\n<ul data-start=\"1279\" data-end=\"1453\" data-is-last-node=\"\" data-is-only-node=\"\">\n<li data-start=\"1279\" data-end=\"1369\">Bachelor s or Master s in Electrical Engineering, Computer Engineering, or related field<\/li>\n<li data-start=\"1370\" data-end=\"1426\">10 years of CPU Architecture<\/li>\n<li data-start=\"1370\" data-end=\"1426\">Hands-on experience with SystemVerilog and UVM<\/li>\n<\/ul>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n<div class=\"absolute\">\n<div class=\"flex items-center justify-center\"><\/div>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n<\/article>\n<div class=\"pointer-events-none h-px w-px\" aria-hidden=\"true\" data-edge=\"true\">* Not able to sponsor.<\/div>\n","protected":false},"excerpt":{"rendered":"<p>Design Verification Engineer RISC-V CPU Development Are you passionate about cutting-edge CPU architecture and ready to take your verification skills to the next level? We re partnering with a global leader in RISC-V processor design to find talented Design Verification Engineers to join their high-impact VLSI team.You ll work alongside seasoned architects and engineers to [&hellip;]<\/p>\n","protected":false},"author":68,"template":"","meta":[],"class_list":["post-1023","awsm_job_openings","type-awsm_job_openings","status-publish","hentry","job-category-semiconductor","job-type-full-time","job-location-remote","pay-depends-on-experience","skills-cpu-development","skills-design-verification","skills-risc-v","travel-no-travel-required"],"_links":{"self":[{"href":"https:\/\/xpeerant.com\/index.php?rest_route=\/wp\/v2\/awsm_job_openings\/1023"}],"collection":[{"href":"https:\/\/xpeerant.com\/index.php?rest_route=\/wp\/v2\/awsm_job_openings"}],"about":[{"href":"https:\/\/xpeerant.com\/index.php?rest_route=\/wp\/v2\/types\/awsm_job_openings"}],"author":[{"embeddable":true,"href":"https:\/\/xpeerant.com\/index.php?rest_route=\/wp\/v2\/users\/68"}],"wp:attachment":[{"href":"https:\/\/xpeerant.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=1023"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}