Expeerant has a long term contract opportunity for a Senior. DV Engineer!

 Explore ways to improve the performance of very high-performance RISC-V processors, across all functions in the CPU core and memory systems.  You will leverage your processor architecture, design, and performance knowledge to work collaboratively with other people in the team, including engineers from the RTL design, verification, and software groups to propose enhancements, optimizations and features based on performance assessment and PPA impact.

Here is what you will do:

• Architect and implement testbenches using UVM-based methods
• Architect and implement Verification Components using UVM-based methods
• Block level verification to validate block performance and adherence to requirements
• Generate and execute verification plan based on specifications
• Coverage definition, implementation, and analysis
• Architect and implement Formal Verification
• Creation of automation tools
• Testing for design performance

Here is the background we hope you have:

• Masters/Bachelor or above degree in electronic/electrical engineering or computer science
• 8+ years of Verification experience
• Industry experience developing testbenches and verification components with SystemVerilog and UVM from scratch
• Deep understanding of event-driven simulator-based modeling techniques
• Low-power implementation (UPF)
• Experience with scripting languages such as Python, Ruby, or Perl
• Solid understanding of chip and/or computer architecture

These would be nice to have but are not required:

• Good written and verbal communication skills
• Good cross site and cross function execution skills